1. Field of the Invention
The present invention relates to the field of circuit design and, more particularly, to routing networks with low skew.
2. Description of the Related Art
Skew is a critical aspect of designing clock networks as well as data networks within a circuit design. In general, skew on a network is the difference in the propagation delays between the fastest terminal load pin and the slowest terminal load pin on that network as measured from the driver, or source, pin. Skew is the result of different electrical lengths, which in turn are a result of different physical lengths and/or different velocities of signal propagation. In consequence, skew has a significant effect on the maximum operating frequency of a circuit design implemented on a programmable logic device such as a field programmable gate array (FPGA).
Typical FPGAs provide a number of high-speed, low-skew wiring resources. These wiring resources are reserved for use by clock networks and, as such, are unavailable to the circuit design for use as data paths. The inclusion of low-skew routing resources is not cost free. Specialized routing resources require silicon area, a quantity that is in limited supply. This area, once used, is not available for other components of the circuit design. Further, these specialized resources must be tested using techniques tailored to the resources. As a result, the inclusion of low-skew routing resources can be expensive, thereby increasing the overall cost of the FPGA.
Because low-skew resources are useful in a variety of different applications it is desirable to include as many low-skew resources as is possible within an FPGA device. The desirability of having a large amount of low-skew resources, however, must be balanced against the cost of providing such resources. Accordingly, it would be beneficial to provide a technique that facilitates the use of general-purpose routing resources for skew-sensitive networks.